GM LIN (J2602-2) Project

1.Open Mx‑VDev.

2.Select File-> Open->Project from the main menu.

3.Use the Open dialog to select the project file:

MxPLT Sample Project LIN.mxp

4.Click Open.

5.Click Edit Harness () to start Mx‑TransIt.

6.In Mx‑TransIt, click on the PLT Test Manager Transform to select it and display its Properties box.

7.Click the “Launch MxPLTConversionTool” Verb to open the tool.

8.Select the “TestCase Generation” tab to generate Scenarios and TestCases dynamically based on selected inputs.

9.Following are the inputs for the TestCase Generation tab of the Mx‑PLT tool.

a.Select TestCase Definition File. Click the browse button () to select the file. Once the input test case definition file is selected, fields in the GUI (Vendor Spec, Bus Interface, Baud Rate, LIN Device Type, LIN Device Clock, and LIN Slave Specific ID) are automatically loaded.

b.Change the Baud Rate as per DUT type.

c.Select LIN Device Type. If the DUT type is slave, then select Slave. If DUT type is master, then select the Master option.

d.LIN Diagnostics. If the DUT supports diagnostic messages, select “Supported.” If the DUT does not support diagnostic messages, select “Not Supported”.

e.Enter a valid LIN Slave Specific ID. The MxPLT, acting as a master node, sends a header as specified here. The ECU responds with data bytes. This field is applicable for LIN Slave DUTs. It is not mandatory for LIN Master DUTs.

f.Click the browse button () to select the Mx‑VDev project folder.

10.Click the Generate TestCases button to generate Scenarios and TestCases for a specific OEM.

Close the Test Conversion Tool, but leave MxVDev running.

1.Open Mx‑VDev.

2.Select File-> Open->Project from the main menu.

3.Use the Open dialog to select the project file:

MxPLT Sample Project LIN.mxp

4.Click Open.

5.The generated Scenarios and TestCases are displayed in the Project Explorer:

6.Select Tools->Regression Test->New.

7.Click the Add button in the Regression Command File dialog.

8.Enter User Details (Optional) in the Test Info panel. Click Next.

9.Click Next in Regression Output Wizard.

10. Click Next in Distribution List.

11. Click Next in Execution Options.

12. In Scenario Query Builder, expand the tree for the Slave folder. Select a Scenario (for example: "7.1.2 Slave Node Bit Time Measurement.mxs") and click Next.

13. Click Finish to open the Save Regression Script dialog.

14. Save the Regression Script File (.mxreg).

15. Click the "Close and Run" button in the Regression Command File dialog:

The Regression Test Progress window shows the progress and pass/fail information of the Regression Test for the selected Scenario.

After completion of the Regression test, the report is automatically displayed.

7.1.2 Slave Node Bit Time Measurement

To measure the slave Node bit time measurement.

7.1.2.1.1  Load 552ohms _1.64nF

To verify the bit time of the Slave DUT is within the specified range under maximum and minimum bus loading conditions and verify that the Slave DUT can respond to a $3D request immediately following a $3C Targeted Reset command for 552 Ω /1.64nF busload

Observe the average bit time.

Acceptance Criteria:

The average bit time shall be between (96 µs (1+/-(0.015 – aging factor of clock)))

7.1.2.1.2  Load 875ohms _5.5nF

To verify the bit time of the Slave DUT is within the specified range under maximum and minimum bus loading conditions and verify that the Slave DUT can respond to a $3D request immediately following a $3C Targeted Reset command for 875 Ω /5.5nF busload.

Observe the average bit time.

Acceptance Criteria:

The average bit time shall be between (96 µs (1+/-(0.015 – aging factor of clock)))

7.1.2.1.3 Load 900ohms _889pF

To verify the bit time of the Slave DUT is within the specified range under maximum and minimum bus loading conditions and verify that the Slave DUT can respond to a $3D request immediately following a $3C Targeted Reset command for 900 Ω /889pF busload.

Observe the average bit time.

Acceptance Criteria:

The average bit time shall be between (96 µs (1+/-(0.015 – aging factor of clock)))

7.1.2.1.4  Load 1.1kohms _4.35nF

To verify the bit time of the Slave DUT is within the specified range under maximum and minimum bus loading conditions and verify that the Slave DUT can respond to a $3D request immediately following a $3C Targeted Reset command for 1.1KΩ /4.35nF busload.

Observe the average bit time.

Acceptance Criteria:

The average bit time shall be between (96 µs (1+/-(0.015 – aging factor of clock)))

7.10.1 ECU Power Loss at Slave  Node

7.10.1.1  Vbatt 8V

To measure the leakage current when the DUT loses battery at Vbatt 8V

Acceptance Criteria:

The measured current shall be less than Ileak batt

7.10.1.2 Vbatt 18V

To measure the leakage current when the DUT loses battery at Vbatt 18V

Acceptance Criteria:

The measured current shall be less than Ileak batt

7.10.2 Bus Wiring Short To Ground - Slave Node

7.10.2 Vbatt 18V

To verify the impedance of the DUT after the LIN bus is shorted to ground

Acceptance Criteria:

The resistance measured at the end of the test shall be

within 1% of that measured at the start of the test.

7.10.4.3 Bus Wiring Short to Battery Slave Device with TxD/RxD Not Accessible

7.10.4.3 Vbatt 12V_Load 1kohms_1nF

To calculate the dominant pulses for rise time,fall time,output voltages or wave shapes values before and after short to battery  with Load 1kohms_1nF

Acceptance Criteria:

There must be no significant difference in rise time, fall time, output voltages or wave shapes for before and after dominant pulses.

7.12.1.2 Normal Battery Voltage Power Operation Slave Device with TxD/RxD Not Accessible

7.12.1.2.1 Vbatt7V_to_18V_Load 1kohms_1nF

To check whether ECU is communicating at Vbatt 7V to 18V with Load 1kohms_1nF

Acceptance Criteria:

The Slave ECU shall respond to the $3D request over the

voltage range of [8.0 to 18.0 V]

7.12.1.2.1 Vbatt18V_to_7V_Load 1kohms_1nF

To check whether ECU is communicating at Vbatt 18V to 7V with Load 1kohms_1nF

Acceptance Criteria:

The Slave ECU shall respond to the $3D request over the

voltage range of [18.0 to 8.0 V]

7.12.2 Battery Power Over-Voltage Operation Slave Device with TxD/RxD Not Accessible

7.12.2.2.1.1  Vbatt18V_to_26.5V_load 1kohms_1nF

To measure r-d transition times and the output voltages for slave mode at Vbatt 18V_to_26.5V with Load 1kohms_1nF

Acceptance Criteria:

If the LIN pin is not recessive, the r-d transition times

and the output voltages

7.12.2.2.1.2 Vbatt26.5V_to_18V_Load 1kohms_1nF

To measure r-d transition times and the output voltages for slave mode at Vbatt 26.5V_to_18V with Load 1kohms_1nF

Acceptance Criteria:

If the LIN pin is not recessive, the r-d transition times

and the output voltages

7.12.3.2 Low Battery Voltage Operation Slave Device with TxD/RxD Not Accessible

7.12.3.2.1.1 Vbatt0V_to_8V_Load 1kohms_1nF

To measure r-d transition times and the output voltages for slave mode at Vbatt 0V_to_8V with Load 1kohms_1nF

Acceptance Criteria:

If the LIN pin is not recessive, the r-d transition times and

the output voltages

7.12.3.2.1.2 Vbatt8V_to_0V_Load 1kohms_1nF

To measure r-d transition times and the output voltages for slave mode at Vbatt 8V_to_0V  with Load 1kohms_1nF

Acceptance Criteria:

If the LIN pin is not recessive, the r-d transition times and

the output voltages

7.4.1.10 Slave Node Termination Resistance

7.4.1.10 Vbatt 12V_Load 30Kohms

To measure the load resistor in the Slave DUT

Acceptance Criteria:

20K <= RDUT <= 60K

7.4.1.11 Slave Node ECU Time Constant and Capacitance Measurement

To measure the capacitance between the LIN pin and ground with Loads.

Note: The capacitance parameters Cin & Cdiff measured by MxPLT include the capacitance of the harness.

User needs to compensate the harness capacitance from the MxPLT measurements.

7.4.1.11 Vbatt 12V_Load 30Kohms

To measure the capacitance between the LIN pin and ground with Load 30kohms

Acceptance Criteria:

90 <= C <=270 pF.

7.4.1.2 Slave Node Voh and Vol Levels Measurement

7.4.1.2.1 Vbatt 8V

To measure the dominant and recessive output voltages of the Slave DUT at Vbatt 8V

Acceptance Criteria:

Measure Logic 1 and Logic 0 of the RSID byte

Logic 1 >= 5.6 V, Logic 0 <= 1.6 V

7.4.1.2.2 Vbatt 18V

To measure the dominant and recessive output voltages of the Slave DUT at Vbatt 18V

Acceptance Criteria:

Measure Logic 1 and Logic 0 of the RSID Byte

Logic 1 >= 13.6 V, Logic 0 <= 3.6 V.

7.4.1.4 Slave Node Vil Level Measurement and Input Threshold Hysteresis (Vih - Vil)

7.4.1.4.1 Vbatt 8V

To measure the recessive input threshold of the Slave DUT at Vbatt 8V

Acceptance Criteria:

The Slave must transition from responding to not responding to the $3D header when: 4.8 V >= Recessive LIN bus voltage >= 3.29 V

7.4.1.4.2 Vbatt 18V

To measure the recessive input threshold of the Slave DUT at Vbatt 18V

Acceptance Criteria:

The Slave must transition from responding to not responding to the $3D header when: 10.8 V >= Recessive LIN bus voltage >= 7.99 V

7.4.1.6 Slave Node Vil Level Measurement and Input Threshold Hysteresis (Vih - Vil)

7.4.1.6.1 Vbatt 8V

To measure the dominant input threshold of the Slave DUT at Vbatt 8V

Acceptance Criteria:

The Slave must transition from responding to not responding to the $3D header when: 4.24 V >= Power Supply 2 >=  2.8 V

7.4.1.6.2 Vbatt 18V

To measure the dominant input threshold of the Slave DUT at Vbatt 18V

Acceptance Criteria:

The Slave must transition from responding to not responding to the $3D header when: 9.54 V >=  Power Supply 2 >=  6.8 V

7.4.1.8 Slave Node Tr-d max and Td-r max Measurement

7.4.1.8.1 Vbatt 8V_Load 875ohms_5.5nF

To measure the recessive to dominant and dominant to recessive transition times of the Slave DUT at Vbatt 8V with Load 875ohms_5.5nF

Acceptance Criteria:

Measure D3 and D4 of the Synch Byte Field

D3 >= 0.417, D4 <= 0.590.

7.4.1.8.2  Vbatt 8V_Load 900ohms_889pF

To measure the recessive to dominant and dominant to recessive transition times of the Slave DUT at Vbatt 8V with Load 900ohms_889pF

Acceptance Criteria:

Measure D3 and D4 of the Synch Byte Field

D3 >= 0.417, D4 <= 0.590.

7.4.1.8.3  Vbatt 18V_Load 875ohms_5.5nF

To measure the recessive to dominant and dominant to recessive transition times of the Slave DUT at Vbatt 18V with Load 875ohms_5.5nF

Acceptance Criteria:

Measure D3 and D4 of the Synch Byte Field

D3 >= 0.417, D4 <= 0.590.

7.4.1.8.4  Vbatt 18V_Load 900ohms_889pF

To measure the recessive to dominant and dominant to recessive transition times of the Slave DUT at Vbatt 18V with Load 900ohms_889pF

Acceptance Criteria:

Measure D3 and D4 of the Synch Byte Field

D3 >= 0.417, D4 <= 0.590.

7.5.1.1 Fixed Clock Slave Node

7.5.1.1.1  Max Bit Sample Timing Vbatt12V_ Load 875ohms_5.5nF

To measure the maximum bit sample point for slave mode with load 875ohms_5.5nF

Acceptance Criteria:

Max_Sample_Point must be <= 63 μsec (10/16 bit times + 1.5%)

7.5.1.1.1  Max Bit Sample Timing Vbatt12V_ Load 900ohms_889pF

To measure the maximum bit sample point for slave mode with load 900ohms_889pF

Acceptance Criteria:

Max_Sample_Point must be <= 63 μsec (10/16 bit times + 1.5%)

7.5.1.1.2 Min Bit Sample Timing Vbatt12V_ Load 875ohms_5.5nF

To measure the minimum bit sample point for slave mode with load 875ohms_5.5nF

Acceptance Criteria:

Min_Sample_Point must be >= 133 μsec (1 7/16 bit times - 1.5%)

7.5.1.1.2 Min Bit Sample Timing Vbatt12V_ Load 900ohms_889pF

To measure the minimum bit sample point for slave mode with load 900ohms_889pF

Acceptance Criteria:

Min_Sample_Point must be >= 133 μsec (1 7/16 bit times - 1.5%)

7.5.1.2 Autobauding Slave Node

7.5.1.2.1  Max Bit Sample Timing Vbatt12V_ Load 875ohms_5.5nF

To measure the maximum bit sample point for slave mode with load 875ohms_5.5nF

Acceptance Criteria:

Max_Sample_Point must be <= 64 μsec (10/16 bit times + 2.0%)

7.5.1.2.1  Max Bit Sample Timing Vbatt12V_ Load 900ohms_889pF

To measure the maximum bit sample point for slave mode with load 900ohms_889pF

Acceptance Criteria:

Max_Sample_Point must be <= 64 μsec (10/16 bit times + 2.0%)

7.5.1.2.2  Min Bit Sample Timing Vbatt12V_ Load 875ohms_5.5nF

To measure the minimum bit sample point for slave mode with load 875ohms_5.5nF

Acceptance Criteria:

Min_Sample_Point must be >= 133 μsec (1 7/16 bit times - 2.0%)

7.5.1.2.2  Min Bit Sample Timing Vbatt12V_ Load 900ohms_889pF

To measure the minimum bit sample point for slave mode with load 900ohms_889pF

Acceptance Criteria:

Min_Sample_Point must be >= 133 μsec (1 7/16 bit times - 2.0%)

7.7.1 Loss of ECU Ground at Slave Node

7.7.1.1  Vbatt 8V

To measure the leakage current when the DUT loses ground at Vbatt 8V

Acceptance Criteria:

The measured leakage current shall be less than Ileak gnd

7.7.1.2 Vbatt 18V

To measure the leakage current when the DUT loses ground at Vbatt 18V

Acceptance Criteria:

The measured leakage current shall be less than Ileak gnd

7.1.1 Master Node Bit Time Measurement

This test verifies the bit time of the Master DUT is within the specified range under maximum and minimum bus loading conditions.

7.1.1.1 Load 1.33kohms_1.59nF

Rload = 1.33Kohm

Cload = 1.59nF

Acceptance Criteria:

The average bit time shall be between (96 us (1+/-

(0.005 – aging factor of clock)))

7.1.1.2 Load 4kohms_5.5nF

Rload = 4Kohm

Cload = 5.5nF

Acceptance Criteria:

The average bit time shall be between (96 us (1+/-

(0.005 – aging factor of clock)))

7.1.1.3 Load 20kohms_889pF

Rload = 20Kohm

Cload = 889nF

Acceptance Criteria:

The average bit time shall be between (96 us (1+/-

(0.005 – aging factor of clock)))

7.1.1.4 Load 60kohms_4.35nF

Rload = 60Kohm

Cload = 4.35nF

Acceptance Criteria:

The average bit time shall be between (96 us (1+/-

(0.005 – aging factor of clock)))

7.4.1.1 Master Node Voh and Vol Levels Measurement

This test verifies the dominant and recessive output voltages of the Master DUT are within the specified range under maximum and minimum supply voltages.

7.4.1.1.1 Vbatt 8V

Vecu =  8V

Acceptance Criteria:

Measure Logic 1 and Logic 0 of the Synch Byte ,

Logic 1 >= 5.6 V, Logic 0 <=1.6 V

7.4.1.1.2 Vbatt 18V

Vecu = 18V

Acceptance Criteria:

Measure Logic 1 and Logic 0 of the Synch Byte ,

Logic 1 >= 13.6 V, Logic 0<=3.6 V

7.4.1.3 Master Node Vih Level Measurement

This test verifies the recessive input threshold of the Master DUT is within the specified range under maximum and minimum supply voltages

7.4.1.3.1 Vbatt 8V

Vecu =  8V

Acceptance Criteria:

The Master must transition from waking to not waking in response to the wake up message when: 4.8 V >= Recessive LIN bus voltage >=3.29 V

7.4.1.3.2 Vbatt 18V

Vecu =  18V

Acceptance Criteria:

The Master must transition from waking to not waking in response to the wake up message when: 10.8 V >= Recessive LIN bus voltage >=7.99 V

7.4.1.5 Master Node Vil Level Measurement and Input Threshold Hysteresis (Vih - Vil)

This test verifies the dominant input threshold of the Master DUT is within the specified range under maximum and minimum supply voltages.

7.4.1.5.1 Vbatt 8V

Vecu =  8V

Acceptance Criteria:

The Master must transition from waking to not waking in response to the wake up message when: 4.24 V >= Power Supply 2 >= 2.8 V

7.4.1.5.2 Vbatt 18V

Vecu =  18V

Acceptance Criteria:

The Master must transition from waking to not waking in response to the wake up message when: 9.54 V >= Power Supply 2 >= 6.8 V

7.4.1.7 Master  Node Tr-d max and Td-r max Measurement

This test verifies the recessive to dominant and dominant to recessive transition times of the Master DUT are within the specified range under maximum and minimum supply voltages.

7.4.1.7.1 Vbatt 8V_Load 4kohms_5.5nF

Vecu = 8V

Rload = 4Kohm

Cload = 5.5nF

Acceptance Criteria:

Measure D3 and D4 of the Synch Byte Field.

D3 >= 0.417, D4 <= 0.590.

7.4.1.7.2 Vbatt 8V_Load 20kohms_889pF

Vecu = 8V

Rload = 20Kohm

Cload = 889pF

Acceptance Criteria:

Measure D3 and D4 of the Synch Byte Field.

D3 >= 0.417, D4 <= 0.590.

7.4.1.7.3 Vbatt 18V_Load 4kohms_5.5nF

Vecu = 18V

Rload = 4Kohm

Cload = 5.5nF

Acceptance Criteria:

Measure D3 and D4 of the Synch Byte Field.

D3 >= 0.417, D4 <= 0.590.

7.4.1.7.4 Vbatt 18V_Load 20kohms_889pF

Vecu = 18V

Rload = 20Kohm

Cload = 889pF

Acceptance Criteria:

Measure D3 and D4 of the Synch Byte Field.

D3 >= 0.417, D4 <= 0.590.

7.10.1 ECU Power Loss – Master Node

This test verifies the leakage current when the DUT loses battery is within the specified range under maximum and minimum supply voltage conditions.

7.10.1.1Vbatt 8V

Vecu = 8V

Acceptance Criteria:

The measured current shall be less than Ileak batt specified in Table 6

of SAE J2602-1  

7.10.1.2Vbatt 18V

Vecu = 18V

Acceptance Criteria:

The measured current shall be less than Ileak batt specified in Table 6 of SAE J2602-1

7.10.2 Bus Wiring Short to Ground – Master Node

This test verifies the impedance of the DUT after the LIN bus is shorted to ground is within 1% of the impedance prior to the shorting event.

Acceptance Criteria:

The resistance measured at the end of the test shall be within 1% of that measured at the start of the test.

7.12.1.2 Normal Battery Voltage Power Operation Master  Device with TxD_RxD Not Accessible

MASTER NORMAL BATTERY VOLTAGE OPERATING RANGE WITH TXD/RXD NOT ACCESSIBLE

This test verifies the operating voltage range of the DUT.

7.12.1.2.2.1Vbatt 7V_to_18V_Load 20kohms_1nF

Vecu Range =7V-18V

Acceptance Criteria:

The Master ECU shall respond to the Wake-up Request over the voltage range of [8.0 to 18.0 V]

7.12.1.2.2.2Vbatt 18V_to_7V_Load 20kohms_1nF

Vecu Range =18V-7V

Acceptance Criteria:

The Master ECU shall respond to the Wake-up Request over the voltage range of [18.0 to 8.0 V]

7.12.2.2.2 Battery Power Over-Voltage Operation Master  Device with TxD_RxD Not Accessible

This test verifies the DUT either operates within the specification or goes into the passive mode when the supply voltage is between 18 and 26.5V.

7.12.2.2.2.1Vbatt 18V_to_26.5V_Load 20kohms_1nF

Vecu Range =18V-26.5V

Acceptance Criteria:

If the LIN pin is not recessive, the r-d transition times and the output voltages must meet the requirements specified in Table 37 of SAE J2602-2 document.

7.12.2.2.2.2Vbatt 26.5V_to_18V_Load 20kohms_1nF

Vecu Range =26.5V-18V

Acceptance Criteria:

If the LIN pin is not recessive, the r-d transition times and the output voltages must meet the requirements specified in Table 37 of SAE J2602-2 document.

7.12.3.2.2 Low Battery Voltage Operation Master Device with TxD_RxD Not Accessible

Low battery voltage operation.

7.12.3.2.2.1Vbatt 0V_to_8V_Load 20kohms_1nF

Vecu Range =0V-8V

Acceptance Criteria:

If the LIN pin is not recessive, the r-d transition times and the output voltages must meet the requirements specified in Table 37 of SAE J2602-2 document.

7.12.3.2.2.2Vbatt 8V_to_0V_Load 20kohms_1nF

Vecu Range =8V-0V

Acceptance Criteria:

If the LIN pin is not recessive, the r-d transition times and the output voltages must meet the requirements specified in Table 37 of SAE J2602-2 document.

7.4.1.11 Master Node ECU Time Constant and Capacitance Measurement

This test measures the capacitance between the LIN pin and ground.

Note: The capacitance parameters Cin & Cdiff measured by MxPLT include the capacitance of the harness.

User needs to compensate the harness capacitance from the MxPLT measurements.

Acceptance Criteria:

90 <= C <=2450 pF.

7.4.1.9 Master  Node Termination Resistance

This test verifies the load resistor in the Master DUT is within the specified range.

Acceptance Criteria:

900 <= RDUT <= 1100

7.7.1 Loss of ECU Ground at Master Node

This test verifies the leakage current when the DUT loses ground is within the specified range under maximum and minimum supply voltage conditions.

7.7.1.1Vbatt 8V

Vecu = 8V

Acceptance Criteria:

The measured leakage current shall be less than Ileak gnd specified in Table 6 of J2602-1

7.7.1.2Vbatt 18V

Vecu = 18V

Acceptance Criteria:

The measured leakage current shall be less than Ileak gnd specified in Table 6 of J2602-1