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Ford LIN Project

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Setup Diagram for Ford LIN Project

Test Name	Test Description	Observation
DLPL_LIN_03_001_7.5.1.1_UART Synchronization	This test verifies the Sample Point of the DUT is within the specified range by shifting a dominant to recessive edge until the message is no longer received properly.
7.5.1.1.1 Fixed clock Max Bit sample timing	Fixed Clock Slave Node
7.5.1.1.1.1Vbatt 12V_Load 875ohms_5.5nF	Rload = 875ohms Cload = 5.5nF Start Bit Time = 70us Do Bit Time = 122us	Acceptance Criteria: Max_Sample_Point must be <= 63 μsec (10/16 bit times + 1.5%)
7.5.1.1.1.2Vbatt 12V_Load 900ohms_889pF	Rload = 900ohms Cload = 889pF Start Bit Time = 70us Do Bit Time = 122us	Acceptance Criteria: Max_Sample_Point must be <= 63 μsec (10/16 bit times + 1.5%)
7.5.1.1.2.1Vbatt 12V_Load 875ohms_5.5nF	Rload = 875ohms Cload = 5.5nF Start Bit Time=125us Do Bit Time = 67us	Acceptance Criteria: Min_Sample_Point must be >= 133 μsec (1 7/16 bit times - 1.5%)
7.5.1.1.2.2Vbatt 12V_Load 900ohms_889pF	Rload = 900ohms Cload = 889pF Start Bit Time=125us Do Bit Time = 67us	Acceptance Criteria: Min_Sample_Point must be >= 133 μsec (1 7/16 bit times - 1.5%)
7.5.1.2.1 Autobauding Slave Node Max Bit Sample Timing	Autobauding Slave Node
7.5.1.2.1.1Vbatt 12V_Load 875ohms_5.5nF	Rload = 875ohms Cload = 5.5nF Start Bit Time = 70us Do Bit Time = 122us	Acceptance Criteria: Max_Sample_Point must be <= 64 μsec (10/16 bit times + 2.0%)
7.5.1.2.1.2Vbatt 12V_Load 900ohms_889pF	Rload = 900ohms Cload = 889pF Start Bit Time = 70us Do Bit Time = 122us	Acceptance Criteria: Max_Sample_Point must be <= 64 μsec (10/16 bit times + 2.0%)
7.5.1.2.2 Autobauding Slave Node Min Bit Sample Timing	Min Bit Sample Timing Slave Node
7.5.1.2.2.1Vbatt 12V_Load 875ohms_5.5nF	Rload = 875ohms Cload = 5.5nF Start Bit Time=125us Do Bit Time = 67us	Acceptance Criteria: Min_Sample_Point must be >= 133 μsec (1 7/16 bit times – 2.0%)
7.5.1.2.2.2Vbatt 12V_Load 900ohms_889pF	Rload = 900ohms Cload = 889pF Start Bit Time=125us Do Bit Time = 67us	Min_Sample_Point must be >= 133 μsec (1 7/16 bit times – 2.0%)
DLPL_LIN_06_002_5.5_ Slave Maximum Transmission Time	The TResponse_Maximum value in which a slave node can complete its response shall be identified in its Node Capability File. In the event a value is not provided in the Node Capability File, the Master node shall presume a value of TResponse_Maximum as defined in the LIN 2.1 Protocol Specification.
5.5.2 Variation of Length of SYNCH BREAK LOW PHASE	This test verifies that the DUT as slave recognises an ID request with different lengths of SYNCH BREAK LOW PHASE TSYNBRK.
5.5.2.1TSYNBRK is TSYNBRK_MIN	TSYNBRK= TSYNBRK_MIN TSYNDEL = TSYNDEL_MIN TH_Interbyte = 0 (TH_Interbyte is the interbyte space between sync field and identifier)	Acceptance Criteria: The DUT must answer the request.
5.5.2.2 TSYNBRK is TSYNBRK_MAX	TSYNBRK = TSYNBRK_MAX TSYNDEL = TSYNDEL_MIN TH_Interbyte = 0	Acceptance Criteria: The DUT must answer the request.
5.5.2.3 TSYNBRK is 20bits	TSYNBRK = 20bits TSYNDEL = TSYNDEL_MIN TH_Interbyte = 0	Acceptance Criteria: The DUT must answer the request.
5.5.4 Variation of Length of SYNCH BREAK DELIMITER	This test verifies that the DUT as slave recognizes an ID request with different lengths of SYNCH BREAK DELIMITER TSYNDEL.
5.5.4.1 TSYNDEL is TSYNDEL_MAX	TSYNBRK = TSYNBRK_MIN TSYNDEL = TSYNDEL_MAX TH_Interbyte = 0	Acceptance Criteria: The DUT must answer the request.
5.5.4.2 TSYNDEL is10bits	TSYNBRK = TSYNBRK_MIN TSYNDEL = 10bits TH_Interbyte = 0	Acceptance Criteria: The DUT must answer the request.
5.5.6 Variation of Length of Header	This test verifies that the DUT as slave recognizes an ID request with different lengths of the Header THEADER.
5.5.6.1 THEADER is THEADER_NOMINAL	TSYNBRK = TSYNBRK_MIN TSYNDEL = TSYNDEL_MIN TH_Interbyte = 0 THEADER = THEADER_NOMINAL	Acceptance Criteria: The DUT must answer the request.
5.5.6.2 THEADER is THEADER_MAXIMIUM	TSYNBRK = 19bits TSYNDEL = 2bits TH_Interbyte = 6bits THEADER = THEADER_MAXIMUM	Acceptance Criteria: The DUT must answer the request.
5.5.6.3 THEADER is 40bits	TSYNBRK = 15bits TSYNDEL = 3bits TH_Interbyte = 2bits THEADER = 40bits	Acceptance Criteria: The DUT must answer the request.
5.5.6.4 TH_Interbyte is 13 bits	TSYNBRK = TSYNBRK_MIN TSYNDEL = TSYNDEL_MIN TH_Interbyte = 13bits THEADER = THEADER_MAXIMUM	Acceptance Criteria: The DUT must answer the request.
5.5.8.1 Length of Frame	This test verifies that the length of TFRAME_MAXIMUM is not exceeded by the DUT’s in-frame-response space and interbyte spaces. Header size = max Data Frame size = 8 SyncBreak length = 19bits SyncDelimiter length=8bits THInterbyte = 0	Acceptance Criteria: The DUT must answer the request with TFRAME_NOMINAL + (THeader_Maximum – THeader_Nominal) ≤ TFrame ≤ TFRAME_MAXIMUM
DLPL_LIN_07_001_7.2.1_Wakeup strategy	Wakeup strategy
7.2.1.2 Wake-Up request to the Slave	This test verifies the ability of the Slave node to receive a wake-up request and to process it upon reception
7.2.1.2.1 Wake-Up request to the Slave_29us	The Test Tool as Master sends a wakeup request for 29uS.	Acceptance Criteria: DUT must not transmit any of its messages.
7.2.1.2.2 Wake-Up request to the Slave _250us	The Test Tool as Master sends a wakeup request for 250uS.	Acceptance Criteria: DUT must transmit the $3D response data.
7.2.1.2.3 Wake-Up request to the Slave_1ms	The Test Tool as Master sends a wakeup request for 1mS.	Acceptance Criteria: DUT must transmit the $3D response data.
7.2.1.2.4 Wake-Up request to the Slave_5ms	The Test Tool as Master sends a wakeup request for 5mS.	Acceptance Criteria: DUT must transmit the $3D response data.
7.2.1.3 Transmit a Wake-Up Request	This test verifies the ability of a slave node to transmit a wake-up request. This test is only applicable to slaves which have wake-up inputs that will generate a LIN bus wake-up. Activate a local wake-up input in the DUT so that a wake-up is generated	Acceptance Criteria: The wakeup pulse length must be 250us < t < 5mS
7.2.1.4 Repeat Wake-Up request when no response by Master	This test verifies the ability of the slave node to resend the wake-up request when there is no response from a master after a wake-up request. This test is only applicable to slaves which have wake-up inputs that will generate a LIN bus wake-up. Activate a local input in the DUT that generates a Wake-up pulse on the LIN Bus.	Acceptance Criteria: DUT must transmit the wake-up requests. 150ms < Twu1 < 300ms 1.5s < Twu2 < 3s After the transmission of the 6th Wake-up pulse monitor the bus for 4 more s to check whether the DUT transmits any more wake-up pulse.
7.2.1.5 Wake-Up Request from Slave followed by a Frame Header from Master	This test verifies the behavior of the slave on receiving the Frame Header from the Master for a Wake-Up request. This test is only applicable to slaves which have wake-up inputs that will generate a LIN bus wake-up. Activate a local wake-up input in the DUT	Acceptance Criteria: DUT must transmit a Wake-Up request on the LIN bus.
DLPL_LIN_07_002_7.2.2_Timeout and sleep commands	The master shall always issue a sleep command when power down of the bus is required, All slaves must implement both the timeout and sleep command.
7.2.2.3 Sleep Mode after Bus Idle	This test verifies the ability of the slave node to enter the sleep mode when the bus is idle for more than 4 s.
7.2.2.3.1 Sleep Mode after Bus Idle		Acceptance Criteria: DUT must go to the quiescent current level specified in the component specification within 60 s unless otherwise specified in the CTS.
7.2.2.3.2 Sleep Mode after Bus Idle		Acceptance Criteria: DUT must go to the quiescent current level specified in the component specification within 60 s unless otherwise specified in the CTS.
7.2.2.3.3 Sleep Mode after Bus Idle	Ensure that there is no message traffic on the bus.	Acceptance Criteria: DUT must go to the quiescent current level specified in the component specification within 60 s unless otherwise specified in the CTS.
7.2.2.4 Sleep Mode Entered with LIN Bus Shorted to Ground	Sleep Mode Entered with LIN Bus Shorted to Ground (DUT as Slave)
7.2.2.4.1 LIN Bus Shorted to Ground		Acceptance Criteria: DUT must go to the quiescent current level specified in the component specification within 60 s unless otherwise specified in the CTS
7.2.2.4.2 LIN Bus Shorted to Ground		Acceptance Criteria: DUT must go to the quiescent current level specified in the component specification within 60 s unless otherwise specified in the CTS
7.2.2.4.3 LIN Bus Shorted to Ground		Acceptance Criteria: DUT must go to the quiescent current level specified in the component specification within 60 s unless otherwise specified in the CTS
7.2.2.2 Receive Command Frame Sleep Mode Command	This test verifies the ability of the slave node to receive a command frame. The command frame type 'Sleep Mode Command' is checked in this test, this frame is used to broadcast the sleep mode to all bus nodes.	Acceptance Criteria: The current drawn by the DUT must go to its specified quiescent current level within 10 sec unless otherwise specified in the component specification.
DLPL_LIN_15_(001 – 006 & 008 – 010)_5.4.1_SAE J2602 Status Byte	All Slaves are required to report the J2602 Status byte and have stabilized the meaning of the APINFOx bits.
5.4.1.1CorruptParity	Send a $3D Response with the ID Parity bits corrupted	Acceptance Criteria: Status Byte returned by the DUT must be (111x xxxx).
5.4.1.2CorruptStopBit	Send a slave specific command message ID and Data for the DUT and corrupt the Stop bit (transmit a dominant) of the last data byte in the frame.	Acceptance Criteria: Status Byte returned by the DUT must be (110x xxxx).
5.4.1.3 CorruptChecksum	Send a $3C Targeted Reset with a corrupted checksum to the DUT	Acceptance Criteria: Status Byte returned by the DUT must be (101x xxxx).
5.4.1.4 CorruptSynByte	Send a $3D Response with sync byte = x. Repeat the steps for x=1 to 255	Acceptance Criteria: Status Byte returned by the DUT must be (100x xxxx) if the device has a fixed clock. Alternatively, if the device is performing autobauding and the SYNC byte was not $55, the Status Byte is ignored but a valid response shall be sent by the DUT..
5.4.1.5 CorruptNAD	Send a $3D Response and corrupt bit 6 (send a dominant) of the NAD byte sent by the DUT.	Acceptance Criteria: Status Byte returned by the DUT must be (100x xxxx).
5.4.1.6 SAE J2602 Status Byte	Combination of all corruption(parity, checksum,NAD) except sync byte	Acceptance Criteria: Checking for the correct response.
DLPL_LIN_06_003 Inter-byte space	Each inter-byte space shall be in between 0 and 8 bit times. The response space shall be between 0 and 8 bit times. The total transmission time is the sum of the header, response space and the response shall be between TFrame_Minimum and TFrame_Maximum as defined in the LIN 2.1 Protocol Specification.	Acceptance Criteria: The inter-byte space shall be less than the 764 us for 10.417kbps.
DLPL_LIN_07_006 Wake Slave Local Event	Generate a slave wake-up trigger and monitor the start-up timing on the LIN net using an oscilloscope or a Network Analyzer.	Acceptance Criteria: The slave shall issue a wake-up within 50ms of the Local event.
DLPL_LIN_07_007 Wake Slave Network Event	Wake-up the bus with and measure the timing between the first header and the first valid response from the slave using a Network Analyzer.	Acceptance Criteria: The slave shall begin responding to the header with valid data within: 100mS for slaves that wake from local events or 250mS for slaves that wake from ignition or Buss traffic only.
DLPL_LIN_07_008 Slave Sends the First Response	Power-up the bus with and measure the timing between the power on event and the first valid response from the slave using a Network Analyzer.	Acceptance Criteria: The slave shall begin responding to the header with valid data within: 100mS for slaves that wake from local events or 250mS for slaves that wake from ignition or Buss traffic only.
DLPL_LIN_11_001_7.10.1 ECU Power Loss	ECUs shall not interfere with normal communication among the remaining bus ECUs during a loss of power (or low voltage) condition. Upon return of power, normal operation shall resume without any operator intervention within a time specified in the "Wake-Up Timing" section. This test verifies the leakage current when the DUT loses battery is within the specified range under maximum and minimum supply voltage conditions.
7.10.1.1ECU Power Loss_Vbatt 8V	Vecu = 8V	Acceptance Criteria: The measured current shall be less than Ileak batt specified in Table 6 of SAE J2602-1
7.10.1.2ECU Power Loss_Vbatt 18V	Vecu = 18V	Acceptance Criteria: The measured current shall be less than Ileak batt specified in Table 6 of SAE J2602-1
DLPL_LIN_11_002_7.10.2 Bus Wiring Short to Ground	Network data communications may be interrupted but there shall be no damage to any ECU when the bus is shorted to ground. A network impedance of less than 50 ohms between the bus and ground shall be considered a short to ground and continued communications are not guaranteed or required. Upon removal of the fault, normal operation shall resume without any operator intervention within 1 second.
7.10.2Bus Wiring Short to Ground_Vbatt 18V	This test verifies the impedance of the DUT after the LIN bus is shorted to ground is within 1% of the impedance prior to the shorting event.	Acceptance Criteria: The resistance measured at the end of the test shall be within 1% of that measured at the start of the test.
DLPL_LIN_11_003_7.10.4 Bus wiring short to battery	Network data communications may be interrupted but there shall be no damage to any device when the bus is shorted to positive battery less than 26.5 volts (Vbatt < 26.5 volts). A network impedance of less than 50 ohms between the bus and battery shall be considered a short and continued communications are not guaranteed or required. Upon removal of the fault, normal operation shall resume without any operator intervention within 1 second.
7.10.4.3.1Device with TxD_RxD Not Accessible	This test verifies the characteristics of the output driver of the DUT after the LIN bus is shorted to battery are the same as they were prior to the shorting event.	Acceptance Criteria: Compare the before and after dominant pulses. There must be no significant difference in rise time, fall time, output voltages or wave shape.
DLPL_LIN_11_005_7.4.1.6 Ground offset voltage	DLPL_LIN_11_005 - Ground offset voltage Ground offset voltage limits at the ECU, specified as 0.1 x Vbatt ECU, must be maintained over the entire range of 8 < Vbatt ECU < 26.5 volts. Set VBatt to 12 volts. Apply a voltage supply of ± 1.2 V (± 0.1 V)	Acceptance Criteria: Communication according to the LDF schedule table shall continue without any errors.
DLPL_LIN_12_001_7.12.1 Normal Battery Voltage Power Operation Slave Device with TxD_RxD Not Accessible
7.12.1.2.1.1Vbatt 8.5V_to_18V_Load 1kohms_1nF	To check whether ECU is communicating at Vbatt 8.5V to 18V with Load 1kohms_1nF	Acceptance Criteria: The Slave ECU shall respond to the $3D request over the voltage range of [8.5 to 18.0 V]
7.12.1.2.1.2Vbatt 18V_to_8.5V_Load 1kohms_1nF	To check whether ECU is communicating at Vbatt 18V to 8.5V with Load 1kohms_1nF	Acceptance Criteria: The Slave ECU shall respond to the $3D request over the voltage range of [18.0 to 8.5 V]
DLPL_LIN_12_002_7.12.2 Normal_Passive mode at high voltage
7.12.2.2.1.1Device with TxD_RxD Not Accessible_Vbatt 18V_to_26.5V_Load 1kohms_1nF	To measure r-d transition times and the output voltages for slave mode at Vbatt 18V_to_26.5V with Load 1kohms_1nF	Acceptance Criteria: If the LIN pin is not recessive, the r-d transition times and the output voltages must meet the requirements specified in Table 37 of SAE J2602-2 document.
7.12.2.2.1.2Device with TxD_RxD Not Accessible_Vbatt 26.5V_to_18V_Load 1kohms_1nF	To measure r-d transition times and the output voltages for slave mode at Vbatt 26.5V_to_18V with Load 1kohms_1nF	Acceptance Criteria: If the LIN pin is not recessive, the r-d transition times and the output voltages must meet the requirements specified in Table 37 of SAE J2602-2 document.
DLPL_LIN_12_003_7.7.1 Leakage current limits
7.7.1.1Loss of ECU Ground_8V	To measure the leakage current when the DUT loses ground at Vbatt 8V	Acceptance Criteria: The measured leakage current shall be less than Ileak gnd
7.7.1.2Loss of ECU Ground_18V	To measure the leakage current when the DUT loses ground at Vbatt 18V	Acceptance Criteria: The measured leakage current shall be less than Ileak gnd
DLPL_LIN_12_004_7.12.2 Over voltage resistability	Same as DLPL_LIN_12_002_7.12.2 Normal_Passive mode at high voltage
DLPL_LIN_12_005_7.12.3 Low Battery Voltage Operation Slave Device with TxD_RxD Not Accessible
7.12.3.2.1.1Vbatt 0V_to_8.5V_Load 1kohms_1nF	To measure r-d transition times and the output voltages for slave mode at Vbatt 0V_to_8.5V with Load 1kohms_1nF	Acceptance Criteria: If the LIN pin is not recessive, the r-d transition times and the output voltages must meet the requirements specified in Table 37 of SAE J2602-2 document.
7.12.3.2.1.2Vbatt 8.5V_to_0V_Load 1kohms_1nF	To measure r-d transition times and the output voltages for slave mode at Vbatt 8.5V_to_0V with Load 1kohms_1nF	Acceptance Criteria: If the LIN pin is not recessive, the r-d transition times and the output voltages must meet the requirements specified in Table 37 of SAE J2602-2 document.

Test Name	Test Description	Observation
DLPL_LIN_06_001_5.5_Master Maximum Transmission Time	Each frame transmission time must be within the range of TFrame_Nominal and TFrame_Maximum. The publisher of the frame must support a maximum frame transmission time of less than TFrame_Maximum.
5.5.1 Master Maximum Transmission Time	This test verifies that the DUT as Master transmits the correct length of the SYNCH BREAK LOW PHASE TSYNBRK as defined in the LIN specification.	Acceptance Criteria: TSYNBRK >=TSYNBRK_MIN
5.5.3 Length of SYNCH BREAK DELIMITER	This test verifies that the DUT as Master transmits the correct length of the SYNCH BREAK DELIMITER TSYNDEL.	Acceptance Criteria: TSYNDEL >=TSYNDEL_MIN
5.5.5 Length of Header	This test verifies that the DUT as Master transmits the correct length of the header THEADER.	Acceptance Criteria: (THEADER_NOMIINAL * 0.995) >=THEADER >=THEADER_MAXIMUM
5.5.8.2 Length of Frame	This test verifies that the length of TFRAME_MAXIMUM is not exceeded by the DUT’s in-frame-response space and interbyte spaces.	Acceptance Criteria: The DUT must send the slave response with TFRAME_NOMINAL + (THeader_Maximum – THeader_Nominal) ≤ TFrame ≤ TFRAME_MAXIMUM
DLPL_LIN_07_001_7.2.1_Wakeup strategy	Wakeup strategy
7.2.1.1 Wake-up Request to the Master	This test verifies the ability of the Master node to receive a wake-up request and to process it upon reception.
7.2.1.1.1 Wake-up Request to the Master_29us	The Test Tool as slave sends a wakeup request for 29uS.	Acceptance Criteria: The DUT must not wake-up and transmit its messages.
7.2.1.1.2 Wake-up Request to the Master_250us	The Test Tool as slave sends a wakeup request for 250uS.	Acceptance Criteria: The DUT must receive the wake-up request and initialize the start up routine. The DUT must send out the frame headers to find the root cause for the request between 100 and 110 ms of the dominant to recessive edge of the wake-up.
7.2.1.1.3 Wake-up Request to the Master_1ms	The Test Tool as slave sends a wakeup request for 1mS.	Acceptance Criteria: The DUT must receive the wake-up request and initialize the start up routine. The DUT must send out the frame headers to find the root cause for the request between 100 and 110 ms of the dominant to recessive edge of the wake-up.
7.2.1.1.4 Wake-up Request to the Master_5ms	The Test Tool as slave sends a wakeup request for 5mS.	Acceptance Criteria: The DUT must receive the wake-up request and initialize the start up routine. The DUT must send out the frame headers to find the root cause for the request between 100 and 110 ms of the dominant to recessive edge of the wake-up.
7.2.1.3 Transmit a Wake-Up Request	This test verifies the ability of a slave node to transmit a wake-up request.	Acceptance Criteria: The wakeup pulse length must be 250us < t < 5mS
DLPL_LIN_07_002_7.2.2 Timeout and sleep commands	This test verifies the ability of the Master node to send command frames; the “Sleep Mode Command” is used for this testing.
7.2.2.1Send Command Frame Sleep Mode Command		Acceptance Criteria: The DUT must send the frame without failure and the first data byte must be 0x00. The DUT must not send any more messages.
DLPL_LIN_07_003 Wake Master Local Event	Verify that the master sends the first header 100ms after the detection of a local event.	Acceptance Criteria: The master must transmit the first header within 100ms of a clean ignition signal
DLPL_LIN_07_004 Wake Master Network Event	Verify that the master sends the first header 130ms after the detection of a Bus wakeup Symbol. Only applies to LIN Buses where the slave can wake the master.	Acceptance Criteria: The measured delay must be <= 130mS
DLPL_LIN_07_005 Power On Master	Connect the power to the bus and monitor how it wakes from a power on event.	Acceptance Criteria: The first master header shall be transmitted within 250ms of a clean battery signal and all slaves shall be responding after 100ms from the first header.
DLPL_LIN_11_001_7.10.1 ECU Power Loss	This test verifies the leakage current when the DUT loses battery is within the specified range under maximum and minimum supply voltage conditions.
7.10.1.1ECU Power Loss_Vbatt 8V	Vecu = 8V	Acceptance Criteria: The measured current shall be less than Ileak batt specified in Table 6 of SAE J2602-1
7.10.1.2ECU Power Loss_Vbatt 18V	Vecu = 18V	Acceptance Criteria: The measured current shall be less than Ileak batt specified in Table 6 of SAE J2602-1
DLPL_LIN_11_002_7.10.2 Bus Wiring Short to Ground	Network data communications may be interrupted but there shall be no damage to any ECU when the bus is shorted to ground. A network impedance of less than 50 ohms between the bus and ground shall be considered a short to ground and continued communications are not guaranteed or required. Upon removal of the fault, normal operation shall resume without any operator intervention within 1 second.
7.10.2Bus Wiring Short to Ground 18V	This test verifies the impedance of the DUT after the LIN bus is shorted to ground is within 1% of the impedance prior to the shorting event.	Acceptance Criteria: The resistance measured at the end of the test shall be within 1% of that measured at the start of the test.
DLPL_LIN_11_003_7.10.4 Bus wiring short to battery	Network data communications may be interrupted but there shall be no damage to any device when the bus is shorted to positive battery less than 26.5 volts (Vbatt < 26.5 volts). A network impedance of less than 50 ohms between the bus and battery shall be considered a short and continued communications are not guaranteed or required. Upon removal of the fault, normal operation shall resume without any operator intervention within 1 second.
7.10.4.3.1TxD_RxD not Accessible	This test verifies the characteristics of the output driver of the DUT after the LIN bus is shorted to battery are the same as they were prior to the shorting event.	Acceptance Criteria: Compare the before and after dominant pulses. There must be no significant difference in rise time, fall time, output voltages or wave shape.
DLPL_LIN_11_005_7.4.1.5 Ground Offset Voltage	DLPL_LIN_11_005 - Ground offset voltage Ground offset voltage limits at the ECU, specified as 0.1 x Vbatt ECU, must be maintained over the entire range of 8 < Vbatt ECU < 26.5 volts. Set VBatt to 12 volts. Apply a voltage supply of ± 1.2 V (± 0.1 V)	Acceptance Criteria: Communication according to the LDF schedule table shall continue without any errors.
DLPL_LIN_12_001_7.12.1 Normal Battery Voltage Power Operationn Slave Device with TxD_RxD Not Accessible	MASTER NORMAL BATTERY VOLTAGE OPERATING RANGE WITH TXD/RXD NOT ACCESSIBLE This test verifies the operating voltage range of the DUT.
7.12.1.2.2.1Vbatt 8.5V_to_18V_Load 1kohms_1nF	Vecu Range =8.5V-18V	Acceptance Criteria: The Master ECU shall respond to the Wake-up Request over the voltage range of [8.5 to 18.0 V]
7.12.1.2.2.2Vbatt 18V_to_8.5V_Load 1kohms_1nF	Vecu Range =18V-8.5V	Acceptance Criteria: The Master ECU shall respond to the Wake-up Request over the voltage range of [18.0 to 8.5 V]
DLPL_LIN_12_003_7.7.1 Leakage current limits	This test verifies the leakage current when the DUT loses ground is within the specified range under maximum and minimum supply voltage conditions.
7.7.1.1Loss of ECU Ground_8V	Vecu = 8V	Acceptance Criteria: The measured leakage current shall be less than Ileak gnd specified in Table 6 of J2602-1 .
7.7.1.2Loss of ECU Ground_18V	Vecu = 18V	Acceptance Criteria: The measured leakage current shall be less than Ileak gnd specified in Table 6 of J2602-1 .
DLPL_LIN_12_004_7.12.2 Over voltage resistability	This test verifies the DUT either operates within the specification or goes into the passive mode when the supply voltage is between 18 and 26.5V.
7.12.2.2.2.1Device with TxD_RxD Not Accessible_Vbatt 18V_to_26.5V_Load 20kohms_1nF	Vecu Range =18V-26.5V	Acceptance Criteria: If the LIN pin is not recessive, the r-d transition times and the output voltages must meet the requirements specified in Table 37 of SAE J2602-2 document.
7.12.2.2.2.2Vbatt 26.5V_to_18V_Load 20kohms_1nF	Vecu Range =26.5V-18V	Acceptance Criteria: If the LIN pin is not recessive, the r-d transition times and the output voltages must meet the requirements specified in Table 37 of SAE J2602-2 document.
DLPL_LIN_12_005_7.12.3 Low Battery Voltage Operation Slave Device with TxD_RxD Not Accessible	Low battery voltage operation.
7.12.3.2.1.1Vbatt 0V_to_8.5V_Load 1kohms_1nF	Vecu Range =0V-8.5V	Acceptance Criteria: If the LIN pin is not recessive, the r-d transition times and the output voltages must meet the requirements specified in Table 37 of SAE J2602-2 document.
7.12.3.2.1.2Vbatt 8.5V_to_0V_Load 1kohms_1nF	Vecu Range =8.5V-0V	Acceptance Criteria: If the LIN pin is not recessive, the r-d transition times and the output voltages must meet the requirements specified in Table 37 of SAE J2602-2 document.