Probes and Overrides are powerful debugging tools. You can use them to view or change any Signal in the Harness. Normally only Project Signals are available as outputs, but it can be useful for white-box testing or harness debugging to monitor signals that are not portable across the SIL/HIL boundary. For example, if there is a Transform in the Harness that does not appear to be functioning as intended, you can probe its input or output Signals for debugging.
Probing allows the user to select any port in the Harness and graph it in the Test-Case window.
To probe a port, select Pick Signals from the TestCase menu, or click on the Pick Signals icon on the TestCase form. Then select the All option at the top. This displays a tree of all transforms in the web. Selecting a transform in the tree populates the list below with all ports available in that transform. Note: All ports are displayed including ports that have not been exported.
Highlight the ports you wish to probe, then press the P> button to add the probes to the TestCase.
The signals are added to the TestCase. The signal name is prefixed with the Data Flow (in or out).
Editing the transitions of a Probe is the same as editing normal signals.
Overrides allow you to inject transitions into the middle of the Virtual Wiring Harness overriding the normal flow of data. This functionality is normally only used for debugging when you believe there may be a problem with the normal source of transitions for the Signal (usually another Transform).
Transitions that normally would have been transmitted into the selected port are discarded and instead the transitions from the Override Signal are transmitted.
To override a port, select Pick Signals from the TestCase menu. Select the All radio button. The dialog box displays a tree of all the Transforms in the Harness. Selecting a Transform in the tree populates the list below with all ports available in that Transform.
Highlight the ports you wish to override, then press the O> button to add the overrides to the TestCase.
The Override signals are added to the TestCase. The signal name is prefixed with the Data Flow (in or out).
Editing the transitions of an Override is the same as editing normal signals.
•When a Signal override is included in a TestCase, the Signal is overridden for the entirety of the Scenario (not just the TestCase) and the normal source of transitions for the Signal is not connected.
•If you insert an override at the output port, Transitions inserted at that point are received by all connected ports. If you want it received by only one of connected downstream ports, then insert the override at that port.
•A port cannot be overridden and probed in the same TestCase.